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- (R) – 必读文献(required reading for the
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- (B) – 背景阅读文献(Background reading on the specific topic)
- (F) – 进一步阅读文献(Further reading on the specific topic)
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(P16, R) R. Ronen, A. Mendelson, K.
LAI, S. Lu, F. Pollack, J. P. Shen. Coming
Challenges in Microarchitecture and Architecture. Proceedings of the IEEEE,
Volume: 89, Issue: 3, March 2001.
·
(P9, R) C. Kozyrakis and D.
Patterson, A New Direction for Computer
Architecture Research, Computer, Vol.
31 Issue 11, November 1998.
·
(P12, B) V. Agarwal, H.S.
Murukkathampoondi, S.W. Keckler, and D.C. Burger. Clock Rate Versus IPC: The End of the Road for Conventional
Microarchitectures. Proceedings of the 27th International Symposium on Computer
Architecture (ISCA), Vancouver, Canada,
June 2000.
·
(P16, B) R. Ho, K. Mai, and M. Horowitz.
The Future of Wires. Proceedings of the IEEE,
Volume: 89, Issue: 4, April 2001.
·
(P12, F) A. Allan, D. Edenfeld, W.H. Joyner, A.B. Kahng, M. Rodgers, Y. Zorian.
2001 Technology Roadmap for
Semiconductors. IEEE Computer, Volume: 35, Issue: 1, January 2001.
(International Roadmap for Semiconductors (ITRS) at http://public.itrs.net/,
sponsored by Semiconductor Industry Association (SIA) and other associations in
Europe, Japan, and Korea. See the 2003 Edition or newer.)
·
(P6, F) S. Hamilton, Taking Moore's Law into the Next
Century, Computer,
Vol. 32 Issue 1, January 1999.
·
(P8, R)
Roger
Espasa, Mateo Valero, and James E. Smith, Vector
Architectures: Past, Present, and Future, ICS '98, Proceedings of the 1998
International Conference on Supercomputing, July 13-17, 1998, Melbourne,
Australia. ACM, 1998.
- (P11, F) C.
Kozyrakis, D. Patterson. Vector
Vs Superscalar and VLIW Architectures for Embedded Multimedia Benchmarks.
Proceedings the 35th International Symposium on Microarchitecture,
Instabul, Turkey, November 2002.
- (P12, F) B.
Khailany, W. Dally, S. Rixner, U. Kapasi, P. Mattson, J. Namkoong, J. Owens,
B. Towles, A. Chang. Imagine: Media
Processing with Streams. IEEE Micro,
Volume: 21, Issue: 2, March 2001.
- (P12, F) R. Espasa, F. Ardanaz, J.
Emer, S. Felix, J. Gago, R. Gramunt, I. Hernandez, T. Juan, G. Lowney, M.
Mattina, A. Seznec. Tarantula: A
Vector Extension to the Alpha Architecture. Proceedings of the 29th
International Symposium on Computer Architecture (ISCA), Anchorage, AL, May
2002.
- (P12,R)
G. Sohi, S.E. Breach and T.N. Vijaykumar, Multiscalar
Processors, in Proc. of the
Int. Symp. on Computer Architecture, pp. 414-425,1995.
- (P10,R)
Pedro Marcuello and Antonio Gonzalez,Thread-Spawning for Speculative Multithreading, Proceedings of
the 8th International Symposium on High-Performance Computer
Architecture(HPCA'02), 2002.
- (P11, F) J.
T. Oplinger, D. L. Heine, and M. S. Lam. In
Search of Speculative Thread-level Parallelism. Proceedings of the 1999
International Conference on Parallel Architectures and Compilation Techniques
(PACT), October1999.
- (P12,R)
Lance Hammond,
Vicky
Wong, Mike Chen, Brian D. Carlstrom, John D. Davis, Ben Hertzberg, Manohar K.
Prabhu, Honggo Wijaya, Christos Kozyrakis, Kunle Olukotun,
Transactional Memory Coherence and Consistency, The
31st Annual International Symposium on Computer Architecture,June 19 - 23, 2004,München,
Germany
- (P12, F)
J. R. Allen, Jr.,B. M. Bass,C. Basso,R. H. Boivie,J. L. Calvignac, IBM
PowerNP network processor: Hardware,software, and applications , IBM
J. RES. & DEV. VOL. 47 NO. 2/3 MARCH/MAY 2003
- (P13, F)
Intel Corporation, Intel
IXP2400
Network Processor -2nd Generation Intel
NPU,
from:http://www.intel.com/design/network/products/npfamily/index.htm
- (P14, R-II)
Marc Tremblay,Jeffrey Chan,
Shailender Chaudhry,The MAJC Architecture:
A Synthesis
of Parallelism and Scalability,
IEEE MICRO,
NOVEMBER–DECEMBER 2000,
pp12-25
- (P21,R-II)J.M.Tendler,
J.S.Dodson, J.S.Fields, Jr.H.Le, B.Sinharoy, Power4
System Microarchitecture, IBM J.RES. & DEV. Vol.46, No.1, January,
2002.
- (P40, R) Michael
Bedford Taylor,Jason Kim,Jason
Miller,The RAW Microprocessor: A Computational Fabric For Software
Circuits and General-Purpose Program, IEEE Micro, MARCH–APRIL 2002
- (P11, R) KATHERINE
COMPTON, SCOTT HAUCK , Reconfigurable Computing:
A Survey of Systems and Software, ACM Computing Surveys, Vol. 34, No. 2,
June 2002, pp. 171–210.
-
6 新型片上存储结构( PIM技术和IRAM技术)*(pdf)
- (P9, F) Maya
Gokhale, Bill Holmes and Ken Iobst, Processing
in Memory: The Terasys Massively Parallel PIM Array, Computer, April
1995.
- (P23,
F) D.PattersonT.Anderson,
N.Cardwell,R.Fromm,K.Keeton,C.Kozyrakis,R.Tomas,
and K.Yelick. A Case for Intelligent
DRAM: IRAM. IEEE Micro,
pp.33-44, April 1997.
- (P12,
B) Yan Solihin, Jaejin
Lee, and Josep Torrellas. Automatic
Code Mapping on an Intelligent Memory Architecture IEEE
Transactions on Computers: special issue on Advances in High Performance
Memory SystemsComputer , November 2001.
- (P12,
B) A. Saulsbury, F. Pong, and A. Nowatzyk. Missing
the Memory Wall: The Case for Processor Memory Integration in Proceedings
of the 23rd International Symposium on Computer Architecture, pages 90--
101, May 1996.
- (P12,B)
D.
Burger, J. Goodman and A. Kagi.,Memory
Bandwidth Limitations of Future Microprocessors,
In Proc. of
the
23rd International Symposium on Computer Architecture (ISCA),
May, 1996.
7
多型处理器结构(pdf)
-
(P12, R) Karthikeyan
Sankaralingam, Ramadass Nagarajan, Haiming Liu, Changkyu Kim, Jaehyuk
Huh, Doug Burger, Stephen W. Keckler, Charles R. Moore,
Exploiting
ILP, TLP, and DLP with the Polymorphous TRIPS Architecture,
Proceedings of the 30th International Symposium on
Computer Architecture (ISCA), San Diego, CA, June 2003.
-
(P12, R)K. Sankaralingam, S.W. Keckler, W.R. Mark, and D.
Burger.,Universal Mechanisms for Data-Parallel Architectures,36th
Annual International Symposium on Microarchitecture (MICRO),
December 2003.
-
(P12, R)J. Huh, D. Burger, and S.W. Keckler., Exploring
the Design Space of Future CMPs, International Symposium on
Parallel Architectures and Compilation Techniques (PACT), pp.
199-210, September, 2001.
-
(P12, R)R. Nagarajan, K. Sankaralingam, D. Burger, and S.W.
Keckler., A Design Space Evaluation of Grid Processor Architectures,
34th Annual International Symposium on Microarchitecture
(MICRO), pp. 40-51, December, 2001.
- (P12, R)
M. Chen, K. Olukotun. TEST:
A Tracer for Extracting Speculative Threads.
Proceedings of International Symposium on Code Generation and Optimization,
San Francisco, CA, March 2003.
- (P10, R)
T. Heil, J. Smith. Relational
Profiling: Enabling Thread Level Parallelism in Virtual Machines.
Proceedings of the 33rd International Symposium on
Microarchitecture, Monterey, CA, December 2000.
- (P12,
R) G. Zilles, G.
Sohi. A
Programmable Co-processor for Profiling.
Proceedings of the 7th International Symposium on High
Performance Computer Architecture, Monterrey, Mexico, January 2001.
- (P12,
R)
S. Sastry, R. Bodik, J. Smith. Rapid
Profiling via Stratified Sampling. Proceedings of the 28th
International Symposium on Computer Architecture, Göteborg, Sweden June
2001.
·
(P11,R)
M. Smith. Overcoming the Challenges to
Feedback-Directed Optimization. Proceedings
of the Workshop on Dynamic and Adaptive Compilation and Optimization,
Boston, MA, January 2000.
·
(P12, R) V. Bala, E. Duesterwald, S. Banerjia. Dynamo:
A Transparent Dynamic Optimization System. Proceedings of the Conference on
Programming Language Design and Implementation, Vancouver, Canada, June 2000.
·
(P19,R)
M. Arnold, S. Fink, D. Grove, M. Hind, and P. Sweeney.
Adaptive optimization in the Jalapeno JVM. ACM
SIGPLAN Conference on Object-Oriented Programming, Systems, Languages, and
Applications (OOPSLA'00),
Minneapolis, Minnesota, October 15-19, 2000.
- [9.4] (P12, R) M. Chen, K. Olukotun. The JRPM System for
Dynamically Parallelizing Java Programs. Proceedings of the 30th
International Symposium on Computer Architecture, San Diego, CA, June 2003.