Project Resources

Candidates	References
From C to RTL: Hardware IP(Accelerators) Design Optmization using HLS Tools	Discrete Wavelet Transformation (DWT), Image Segmentation,etc. PolyBench/C : Matrix Multiplication(MM), Finite Difference Time Domain (FDTD-2D), Symmetric Rank-k Operations (syrk),etc. Chen Zhang, Peng Li, Guangyu Sun, "Optimization FPGA-based Accelerator Design for Deepp Convolutional Neural Netowrks", FPGA 15: Deep Convolutional Neural Networks (CNN). Xilinx Vivado (Including HLS), Get Started. Open-source HLS Tools: LegUp
RTL Design & From RTL to gate optimization using Logic Synthesis tools	David A. Patterson and John L. Hennessy, Computer Organization and Design: The hardware/software interface, 4th edition, Chapter 3, Chapter 4. Appendices : Simple MIPS CPU, Multiplier, Floating Point Multiplier Design Compiler Documents(Logic Design) IEEE Std 1364-2005. Verilog Hardwar Description Language. Piscataway, New Jersey: The IEEE Computer Society, 2005.
From gate to GDSII: Pysical Design Optmization using Layout Tools	IC Compiler Documents

Candidates	References	Benchmarks
Floorplanning	[2].Chapter 10	MCNC Benchmark GSRC Benchmark
Placement	[2].Chapter.11, Selected.Papers	IBM-PLACE 2.0 benchmark suits ISPD98 circuit Benchmark suite
Global Routing	[2].Chapter.12	ISPD 2008 Global Routing benchmark suits
Clock Network Synthesis	[2].Chapter.13	ISPD 2009 Clock Network Synthesis benchmark suits