LSI Design Optimization (LSI設計最適化) |
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| Lecture Time: Wednesday 16:30-18:00 (水曜日 第5時限) | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| Office Hours: Tuesday (火曜日) 15:30 - 17:30, or send your questions to me. (chensong@aoni.waseda.jp) | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| Place: N105 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| TA: Hao Cong (カク 聡, N359),hc.onioncc@gmail.com, ZHU Deming (朱徳明, N318), maxwell@ruri.waseda.jp | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
|
Schedule [lecture notes are downloadable inside the campus] |
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| Lecture | Date | Topic | Availabe | Due |
| 1 | Sept. 28 | Guidance | ppt pdf | |
| 2 | Oct. 5 | verilog basics-1 (Verilog 基礎) | ppt pdf tutorial-1 Test_bench | |
| 3 | Oct. 12 | verilog basics-2 (Verilog 基礎) | ppt pdf tutorial Reading: Nonblocking Assignments | |
| 4 | Oct. 19 | verilog basics-3 (Verilog 基礎) | ppt pdf | |
| 5 | Oct. 26 | Logic Sythesis（論理合成） | ppt pdf synthesis tutoril ProblemSet02 | |
| 6 | Nov. 2 | Timing Issue （タイミング） | ppt pdf Timing.Issue ProblemSet02-Optional A.Simple.Router.Design | |
| 7 | Nov. 9 | Transistors and Gates（トランジスタとゲート） | ppt pdf | |
| Nov. 16 | No Lecture | |||
| Nov. 23 | No Lecture | |||
| 8 | Nov. 26 | Power Issue (電力消費) | ppt pdf The.CMOS.Inverter (Deep analysis of the basic CMOS gate) Exercise | |
| 9 | Nov. 30 | Verilog Basics-4: Design Example 2 | ppt pdf MIPS CPU FF Processor Proposal_template Exercise | |
| 10 | Dec. 7 | DC. Ref. Method. | pdf Exercise | |
| 11 | Dec. 14 | Floorplanning/Placement | ppt pdf Exercise | |
| 12 | Dec. 21 | Clock Tree Synthesis | ppt pdf | |
| Dec. 28 | No Lecture | |||
| Jan. 4 | No Lecture | |||
| 13 | Jan. 11 | Static Timing Analysis | ppt pdf STA:Practical: local Waseda Lib | |
| 14 | Jan. 18 | Manufacturability and Routing | ppt pdf | |
| 15 | Feb. 1, 2 | Project Presentation | schedule Project Submission Guide | |
| how to submit your solutions and reports |
SOLD: Synopsys On-line Documents [Avaiable on servers, or see links below.
IEEE Std 1364-2005. Verilog Hardwar Description Language. Piscataway, New Jersey: The IEEE Computer Society, 2005.(pdf) [Revised in 2001 and reaffirmed, with System Verilog added compatibility, in 2005. If you plan to do any serious work in verilog, you should have a copy of the standard. It is not oly normative, but it includes numerous examples and explanatory notes concering every detail of the language.]
Samir Palnitkar, "Verilog HDL: A Guide to Digital Design and Synthesis", Second Edition, Prentice Hall.
Douglas J. Smith,HDL Chip Design: A Practical Guide for Deisning, Synthesizing and Simulating ASICs and FPGAs using VHDL or Verilog.
Himanshu Bhatnagar, Advanced ASIC Chip Synthesis: Using Synopsys Design Compiler, Physical Compiler and PrimeTime, Kluwer Academic Publishers.
Meil H. E. Weste and David Money Narris, "CMOS VLSI Design: A circuits and Systems Perspective", fourth edition, Addison-Wesley
DesignWare Building Block IP Quick Reference (You should have a copy)
DesignWare Building Block IP User Guide (You should have a copy)
DesignWare Building Block IP Application Notes
Unix Tutorial for Beginners VI Help EMACS Help
Nonblocking Assignments in Verilog Synthesis, Coding Styles That Kill!
Parameterized Models Using Verilog 2001
RTL Coding Styles That Yield Simulation and Synthesis Mismatches
Online Verilog HDL Quick Reference Guide
ITRS executive summary, and design challenges (downloadable from (ITRS)International Technology Roadmap for Semiconductor)