Journal Publications [Home]
  1. Junpeng Wang, Mengke Ge, Bo Ding, Qi Xu, Song Chen, Yi Kang. NicePIM: Design Space Exploration for Processing-In-Memory DNN Accelerators with 3D-Stacked-DRAM. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems . pp.1-14, Accepted, 2023. ( Early Access in IEEE Xplore)
  2. Wenhao Sun, Zhiwei Zou, Deng Liu, Wendi Sun, Song Chen, Yi Kang. Bit-balance: Model-Hardware Co-design for Accelerating NNs by Exploiting Bit-level Sparsity. IEEE Transactions on Computers . Accepted, 2023.
  3. Bo Ding, Jinglei Huang, Qi Xu, Junpeng Wang, Song Chen, Yi Kang. Task modules Partitioning, Scheduling and Floorplanning for Partially Dynamically Reconfigurable Systems with Heterogeneous Resources. ACM Transactions on Design Automation of Electronic Systems. Accepted, 2023.(Early Access ACM Digital library)
  4. Yongtian Bi, Qi Xu, Hao Geng, Song Chen, Yi Kang. AD2VNCS: Adversarial Defense and Device Variation Tolerance in Memristive Crossbar-Based Neuromorphic Computing Systems. ACM Transactions on Design Automation of Electronic Systems. March 2023.(accepted).(Early Access ACM Digital library)
  5. Xiaobing Ni, Mengke Ge, Yongjin Tao, Wendi Sun, Feixiang Duan, Xuefei Bai, Qi Xu, Song Chen, and Yi Kang. BusMap: Application Mapping with Bus Routing for Coarse-Grained Reconfigurable Array. IEEE Transactions on Circuits and Systems II: Express Briefs. March 2023.(accepted).(Full Text in IEEE Xplore)
  6. Wenhao Sun, Deng Liu, Zhiwei Zou, Wendi Sun, Song Chen, and Yi Kang. Sense: Model-Hardware Co-design for Accelerating Sparse CNNs on Systolic Arrays. IEEE Transactions on Very Large Scale Integration Systems (VLSI). January 2023.(accepted).(Full Text in IEEE Xplore).
  7. Yongtian Bi, Qi Xu, Hao Geng, Song Chen, and Yi Kang. Resist: Robust Network Training for Memristive Crossbar-Based Neuromorphic Computing Systems. IEEE Transactions on Circuits and Systems II: Express Briefs. December, 2022. doi: 10.1109/TCSII.2023.3236168.(accepted). (Full Text in IEEE Xplore)
  8. Junpeng Wang, Haitao Du, Bo Ding, Qi Xu, Song Chen, Yi Kang. DDAM: Data Distribution-Aware Mapping of CNNs on Processing-In-Memory Systems. ACM Transactions on Design Automation of Electronic Systems. October, 2022 (accepted). (Full Text in ACM Digital Library)
  9. Ke Hu, Wenhao Sun, Zhongbo Nie, Ran Cheng, Song Chen, and Yi Kang. Real-time infrared small target detection network and accelerator design. Integration, the VLSI Journal. Vol.87, 241-252. 2022.
  10. Bo Ding, Jinglei Huang, Qi Xu, Junpeng Wang, Song Chen, Yi Kang. Memory-aware Partitioning, Scheduling, and Floorplanning for Partially Dynamically Reconfigurable Systems. ACM Transactions on Design Automation of Electronic Systems. 28, 1, Article 7 (January 2023), 21 pages. (Full Text in ACM Digital Library)
  11. Qi Xu, Hao Geng, Tianming Ni, Song Chen, Bei Yu, Yi Kang, and Xiaoqing Wen, "Fortune: A New Fault-Tolerance TSV Configuration in Router-based Redundancy Structure", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems , 2021 (accepted) (Full Text in IEEE Xplore).
  12. Qi Xu, Hao Geng, Song Chen, Bo Yuan, Cheng Zhuo, Yi Kang, Xiaoqing Wen, "GoodFloorplan: Graph Convolutional Network and Reinforcement Learning Based Floorplanning", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems , 2021 (accepted) (Full Text in IEEE Xplore).
  13. Qi Xu, Junpeng Wang, Bo Yuan, Qi Sun, Song Chen, Bei Yu, Yi Kang and Feng Wu, "Reliability-Driven Memristive Crossbar Design in Neuromorphic Computing Systems", IEEE Transactions on Automation Science and Engineering (TASE) , 2021 (accepted)
  14. Mengke Ge, Bingxiao Ni, Song Chen, and Yi Kang, "Generating Brain-Network-Inspired Toplogies for Large-Scale NoCs on Monolithic 3D ICs", IEEE Transactions on Circuits and Systems II: Express Briefs , vol. 69, no. 3, pp. 1552-1556, March,2022. (Full Text in IEEE Xplore)
  15. Mengke Ge, Bingxiao Ni, Qi Xu, Jinglei Huang, Song Chen, Yi Kang, Feng Wu, "Synthesizing Brain-Network-Inspired Interconnections for Large-Scale Network-on-Chips", ACM Transactions on Design Automation of Electronic Systems , 2021 (accepted)
  16. Qi Xu, Wenhao Sun, Song Chen, Yi Kang and Xiaoqin Wen. Cellular Structure Based Fault-Tolerance TSV Configuration in 3D-IC. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol.41, No.5, pp.1196-1208, May 2022. (online, Full Text in IEEE Xplore ) doi: 10.1109/TCAD.2021.3084920
  17. Zhimin Lu, Jue Wang, Zhiwei Li, Song Chen and Feng Wu. A Resource-Efficient Pipelined Architecture for Real-Time Semi-Global Stereo Matching. IEEE Transactions on Circuits and Systems for Video Technology, Vol.32, No.2, pp. 660-673, 2022. (online, Full Text in IEEE Xplore ) doi: 10.1109/TCSVT.2021.3061704.
  18. Song Chen , Mengke Ge, Zhigang Li, Jinglei Huang, Qi Xu, and Feng Wu. Generalized Fault-Tolerance Topology Generation for Application Specific Network-on-Chips. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 39, no. 6, pp. 1191-1204, June 2020.( Full Text in IEEE Xplore )
  19. Song Chen , Jinglei Huang, Xiaodong Xu, Bo Ding, Qi Xu, “Integrated Optimization of Partitioning, Scheduling, and Floorplanning for Partially Dynamically Reconfigurable Systems”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems , October, Vol.39, No.1, pp.199-212, January 2020.(Full Text in IEEE Xplore)
  20. Qi Xu, Song Chen , Hao Geng, Bo Yuan, Bei Yu, Feng Wu, Zhengfeng Huang, “Fault Tolerance in Memristive Crossbar-Based Neuromorphic Computing Systems”, Integration-the VLSI Journal, vol. 70, Jan., pp. 70–79, 2020. ( online).
  21. Qi Xu, Hao Geng, Song Chen , Bei Yu, Feng Wu, “Memristive Crossbar Mapping for Neuromorphic Computing Systems on 3D IC”, ACM Transactions on Design Automation of Electronic Systems (TODAES), vol. 25, no. 1, pp. 8:1–8:19, 2019.
  22. Song Chen, Qi Xu, Bei Yu, “Adaptive 3D-IC TSV Fault Tolerance Structure Generation”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems , 38(5), pp.949-960,2019. (Full Text in IEEE Xplore)
  23. Jinglei Huang, Xiaodong Xu, Nan Wang, Song Chen , "Reconfigurable Topology Synthesis for Application-Specific NoC on Partially Dynamically Reconfigurable Systems", Integration-the VLSI Journal, Volume 65, March 2019, Pages 331-343.
  24. Yan Li, Zhiwei Li, Chen Yang, Wei Zhong, and Song Chen, “High throughput Hardware architecture for accurate semi-global matching”, Integration-the VLSI Journal, Volume 65, March 2019, Pages 417-427.
  25. Nan Wang, Song Chen, Jianmo Ni, Xiaofeng Ling and Yu Zhu, "Security-Aware Task Scheduling Using Untrusted Components in High-Level Synthesis," in IEEE Access, vol. 6, pp. 15663 - 15678, 2018.
  26. Nan Wang, Song Chen, Zhiyuan Ma, Xiaofeng Ling, Yu Zhu, “Integrating Operation Scheduling and binding for functional unit power-gating in high-level synthesis”, Integration-the VLSI Journal, Volume 65, March 2019, Pages 308-321.
  27. Nan Wang, Wei Zhong, Song Chen , Zhiyuan Ma, Xiaofeng Ling, and Yu Zhu, “Power-gating-aware scheduling with effective hardware resources optimization”, Integration-the VLSI Journal, Vol.61, pp.167-177, 2018.
  28. Jinglei Huang, Wei Zhong, Zhigang Li, Song Chen , "Lagrangian relaxation-based routing path allocation for application-specific network-on-chips", Integration-the VLSI Journal, Vol. 61, pp.20-28, 2018.
  29. Qi Xu, Song Chen, "Fast thermal analysis for fixed-outline 3D floorplanning", Integration-the VLSI Journal, September 2017 Vol. 58 No.9, pp.157-167.
  30. Qi Xu, Song Chen , Xiaodong Xu, Bei Yu, "Clustered Fault Tolerance TSV Planning for 3D Integrated Circuits", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. Vol. 36, No.8, pp. 1287-1300, Aug. 2017.(Full Text in IEEE Xplore)
  31. Gan Feng, Lan Yao, Song Chen, "AutoNFT: Architecture Synthesis for Hardware DFT of Length of Coprime-Number Products", Integration-the VLSI Journal, vol. 58, No.6, pp.339-347, June 2017.
  32. Nan Wang, Wei Zhong, Cong Hao, Song Chen, Takeshi Yoshimura, Yu Zhu, "Leakage Power-Aware Scheduling with Dual-Threshold Voltage Design", IEEE Transactions on Very Large Scale Integration Systems (VLSI) vol.24, No.10, pp. 3067-3079,2016. (Full Text in IEEE Xplore)
  33. Jinglei Huang, Song Chen, Wei Zhong, Wenchao Zhang, Shengxi Diao, Fujiang Lin, "Floorplanning and Topology Synthesis for Application Specific Network-on-Chips with RF-Interconnect", ACM Transactions on Design Automation of Electronic Systems 21(3):40,23 pages, 2016.
  34. Qi Xu，Song Chen, Bin Li, “Combining the ant system algorithm and simulated annealing for 3D/2D fixed-outline floorplanning”, Applied Soft Computing, 40:150-160, 2016/03.
  35. Nan Wang, Song Chen, Wei Zhong, Nan Liu, Takeshi Yoshimura, “Mobility Overlap-Removal-Based Leakage Power and Register-Aware Scheduling in High-Level Synthesis”, IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol E97-A, No.8, pp.1-11(accepted), No.8, 2014.
  36. Nan Wang, Song Chen, Cong Hao, Haoran Zhang, and Takeshi Yoshimura, “Leakage Power Aware Scheduling in High-Level Synthesis ”, IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol. E97-A, No.4, pp.940-951, 2014.
  37. Wei Zhong, Song Chen, Bo Huang, Takeshi Yoshimura, and Satoshi Goto, “Floorplanning and Topology Synthesis for Application-Specific Network-on-Chips”, IEICE Transactions on on Fundamentals of Electronics, Communications and Computer Sciences,, Vol. E96-A, No.6, pp. 1174- 1184, 2013.
  38. Nan Liu, Song Chen, and Takeshi Yoshimura, “ Resource-aware Multi-layer Floorplanning for Partially Reconfigurable FPGAs ”, IEICE Transactions on Electronics, Vol.E96-C, No.4, pp 501-510, 2013.
  39. Haiqi WANG, Sheqin DONG, Tao LIN, Song Chen, and Satoshi GOTO, “ Novel Voltage Choice and Min-Cut Based Assignment for Dual-VDD System ”, IEICE Transactions on Fundmentals of Electronics, Communications and Computer Sciences, Vol.E95-A No.12, pp 2208-2219, 2012.
  40. Nan Liu, Song Chen, and Takeshi Yoshimura, “Floorplanning for High Utilization of Heterogeneous FPGAs ”, IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol.E95-A, No.9, pp 1529-1537, 2012.
  41. Wei Zhong, Takeshi Yoshimura, Bei Yu, Song Chen, Sheqin Dong and Satoshi Goto, " Cluster Generation and Network Component Insertion for Topology Synthesis of Application-Specific Network-on-Chips", IEICE Transactions on Electronics, Vol.E95-C, NO.4, pp.535-545, April,2012.
  42. Song Chen, J. Shen, W. Guo, M.F. Chiang, and T. Yoshimura. “ Redundant Via Insertion: Removing Design Rule Conflicts and Balancing Via Density”, IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol.E93-A, No.12, Dec. 2010, pp.2372-2379.
  43. Song Chen and T. Yoshimura. Multi-layer floorplanning for stacked ICs: Configuration number and fixed-outline constraints. Integration, the VLSI journal, 43(4), pp.378-388, 2010. binary package
  44. Song Chen, Liangwei Ge, Mei-Fang Chiang, Takeshi Yoshimura, “ Lagrangian Relaxation Based Inter-Layer Signal Via Assignment for 3-D ICs”, IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol.E92-A, No.4, pp.1080-1087, 2009.
  45. Song Chen and T. Yoshimura, “ Fixed-outline floorplanning: Enumerating block positions and a new objective function for calculating area costs,” IEEE Transactions On CAD of Integrated Circuits and Systems, vol.27, no. 5, pp.858-871, 2008. binary package
  46. Song Chen, S. Dong, X. Hong, and C. Cheng, “Vlsi block placement with alignment constraints,” IEEE Transactions on Circuits and Systems II: Express Briefs , vol. 53, no. 8, pp. 622-626, 2006.
  47. L. Ge, Song Chen, K. Wakabayashi, T. Takenaka, and T. Yoshimura, “ Maxflow scheduling in high-level synthesis,” IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, vol. E90-A, no. 9, pp.1940-1948, 2007.
  48. L. Ge, Song Chen, Y. Nakamura, and T. Yoshimura, “ A synthesis method of general floating-point arithmetic units by aligned partition,” IPSJ Transactions on System LSI Design Methodology, vol.1, pp. 67-77, Aug. 2008.
  49. L. Ge, Song Chen, and T. Yoshimura, “ Exploration of schedule space by random walk,” IPSJ Transactions on System LSI Design Methodology, vol. 2, pp.30-42, Feb. 2009.
  50. S. Dong, X. Hong, Song Chen, and et al, “ Vlsi module placement with pre-placed modules and with consideration of congestion using solution space smoothing,” IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, vol.E86-A, no.12, pp. 3136-3147, 2003.
  51. B. Yu, S. Dong, Song Chen, and S. Goto. “ Voltage and level-shifter assignment driven floorplanning”, IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol.E92-A, No.12:2990-2997, 2009.
  52. Y. Ma, X. Hong, S. Dong, Song Chen, and et al, “ Buffer planning as an integral part of floorplanning with consideration of routing congestion,” IEEE Transactions on CAD of Integrated Circuits and Systems, vol.24, no.4, pp.609-621, 2005.
  53. Song Chen, X. Hong, S. Dong, and et al, “ Fast evaluation of bounded sliceline grid,” Journal of Computer Science and Technology (Springer), vol.19, no.6, pp. 973-980, 2004.
  54. Song Chen, X. HOng, S. Dong, and et al, “ A buffer planning algorithm for chip-level floorplanning,” Science in China Series F-Information Sciences (Springer), vol.47, no.6, pp.763-776, 2004.

Conference Publications

  1. Ke Hu, Tongbo Cao, Yuan Li, Song Chen, and Yi Kang. DALDet: Depth-aware Learning Based Object Detection for Autonomous Driving. 38th AAAI Conference on Artificial Intelligence, Vancouver, Canada, Feb. 2024.
  2. Bing Li, Wendi Sun, Xiaobing Ni, Kaixuan He, Qi Xu*, Song Chen*, Yi Kang. Parallel Multi-objective Bayesian Optimization Framework for CGRA Microarchitecture. IEEE/ACM Proceedings Design, Automation and Test in Europe (DATE), Valencia, Spain, Mar. 25–27, 2024.
  3. Bo Yang, Qi Xu*, Hao Geng, Song Chen, Yi Kang. Miracle: Multi-Action Reinforcement Learning-Based Chip Floorplanning Reasoner. IEEE/ACM Proceedings Design, Automation and Test in Europe (DATE), Valencia, Spain, Mar. 25–27, 2024.
  4. Ziyi Wang, Siting Liu, Yuan Pu, Song Chen, Tsung-Yi Ho, Bei Yu. Realistic Sign-off Timing Prediction via Multimodal Fusion. ACM/IEEE Design Automation Conference (DAC), San Francisco, Jul. 09–13, 2023.
  5. Qiqiao Wu, Wenhao Sun, Junpeng Wang, Xuefei Bai, Feng Zhang, Song Chen, and Yi Kang. A Non-volatile Computing-in-Memory ReRAM Macro using Two-bit Current-Mode Sensing Amplifier. IEEE 10th Non-Volatile Memory Systems and Applications Symposium (NVMSA) , August 2021.
  6. Qi Xu, Junpeng Wang, Hao Geng, Song Chen, and Xiaoqing Wen. Reliability-Driven Neuromorphic Computing Systems Design. Design, Automation & Test in Europe Conference & Exhibition (DATE), Febrary 2021.
  7. Xun Yuan and Song Chen. SaD-SLAM: A Visual SLAM Based on Semantic and Depth Information. IEEE/RSJ International Conference on Intelligence Robots and Systems (IROS), Las Vegas, NV, USA (Virtual), 2020.
  8. Mengke Ge, Qi Xu, Huajie Ruan, Xiaobing Ni, Song Chen, and Yi Kang. Synthesizing A Generalized Brain-inspired Interconnection Network for Large-scale Network-on-chip Systems, The 30th edition of the ACM Great Lakes Symposium on VLSI, Sept., 2020.
  9. Yuting Wu, Bo Ding, Qi Xu, Song Chen，Fault-Tolerant-Driven Clustering for Large Scale Neuromorphic Computing Systems[C]. IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS), Italy, 2020:238-242.
  10. Junpeng Wang, Qi Xu, Bo Yuan, Song Chen, Bei Yu, Feng Wu. Reliability-Driven Neural Network Training for Memristive Crossbar-Based Neuromorphic Computing Systems. IEEE International Symposium on Circuits and Systems, 2020.
  11. Tianzhi Xue, Baicheng Liu, Wenhao Sun, Song Chen∗, Yi Kang, and Feng Wu. Customizing CMOS/ReRAM Hybrid Hardware Architecture for Spiking CNN. 13th IEEE International Conference on ASIC (ASICON). 2019.
  12. Baicheng Liu, Song Chen∗, Yi Kang, and Feng Wu, “An Energy-Efficient Systolic Pipeline Architecture for Binary Convolutional Neural Network”, 13th IEEE International Conference on ASIC (ASICON). 2019.
  13. J. Wang, Z. Li, L. Yao, S. Chen, and F. Wu, Low-Resource Hardware Architecture for Semi-Global Stereo Matching[C]. IEEE International Symposium on Circuits and Systems (ISCAS 2019), Sapporo Japan, May 26-29,2019.
  14. Qi Xu, Song Chen, Bei Yu, Feng Wu, “Memristive Crossbar Mapping for Neuromorphic Computing Systems on 3D IC”, The 28th edition of the ACM Great Lakes Symposium on VLSI(GLSVLSI), pp.451-454, Chicago, USA, May, 2018.
  15. J. Huang, X. Xu, L. Yao and S. Chen, "Reconfigurable topology synthesis for application-specific noc on partially dynamically reconfigurable FPGAs", 2017 ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP), Austin, TX, USA, 2017, pp. 1-8.
  16. Xiaodong Xu, Qi Xu, Jinglei Huang, Song Chen, "An Integrated Optimization Framework for Partitioning, Scheduling and Floorplanning on Partially Dynamically Reconfigurable FPGAs", The 27th edition of the ACM Great Lakes Symposium on VLSI(GLSVLSI), pp.403-406, Alberta, Canada, May, 2017.
  17. Yan Li, Chen Yang, Wei Zhong, Song Chen, “High Throughput Hardware Architecture for Accurate Semi-Global Matching”, ACM/IEEE Asia and Southern Pacific Design Automation Conference(ASPDAC), Jan. 2017.
  18. Gan Feng, Zuyi Hu, Song Chen, Feng Wu, “Energy-Efficient and High-Throughput FPGA-based Accelerator for Convolutional Neural Networks”, IEEE International Conference on Solid-state and Integrated Circuits Technology (ICSICT), Oct. 2016.
  19. Cheng Chen, Song Chen, “High-Throughput Binary Arithmetic Encoder Architecture for CABAC in H.265/HEVC”, 13th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT), Oct. 2016.
  20. Chen Yang, Yan Li, Wei Zhong, Song Chen, Real-Time Stereo Matching Using Guided Image Filter, 26th edition on Great Lakes Symposium on VLSI (GLSVLSI), 2016/5/18-2016/5/20, pp 1-4, Boston, USA.
  21. Wenchao Zhang, Song Chen, Xuefei Bai, Dajiang Zhou, “A Full Layer Parallel QC-LDPC Decoder for WiMAX and Wi-Fi”, IEEE 11th International Conference on ASICs (ASICON), Chengdu,China, November 2015.
  22. Jinglei Huang, Zhigang Li, Wei Zhong and Song Chen* "Lagrangian Relaxation Based Topology Synthesis for Application-Specific Network-on-Chips”, IEEE 11th International Conference on ASICs (ASICON), Chengdu, China, November 2015.
  23. Zhen Meng, Song Chen and Lu Huang, "Irregularly Shaped Voltage Islands Generation with Hazard and Heal Strategy", IEEE 16th International Symposium on Quality Electronic Design (ISQED), San Clara, USA, March, 2015, pp.1-4.
  24. Qi Xu, Song Chen and Bin Li, "Ant system based 3D fixed-outline floor planning," IEEE 12th International Conference on Solid-State and Integrated Circuit Technology (ICSICT), 2014 pp.1-3, October 2014.
  25. Cong Hao, Song Chen, Takeshi Yoshimura, “Network Simplex Method Based Multiple Voltage Scheduling in Power-Efficient High-Level Synthesis”, ACM/IEEE Asia and Soutch Pacific Design Automation Conference (ASP-DAC), Yokohama, Japan, 2013, pp.237-242.
  26. Bo Huang, Song Chen, Wei Zhong, T. Yoshimura, “Application-Specific Network-on-Chip Synthesis with Topology-Aware Floorplanning”, ACM International Symposium on Integrated Circuits and Systems Design (SBCCI), August, 2012
  27. Song Chen, Xiaolin Zhang, Takeshi Yoshimura, “Practically Scalable Floorplanning with Voltage Island Generation”, ACM The International Symposium on Low Power Electronics and Design (ISLPED), July, Redondo, USA, 2012.
  28. Cong Hao, Song Chen, Takeshi Yoshimura , "Port assignment for interconnect reduction in high-level synthesis," VLSI Design, Automation, and Test (VLSI-DAT), IEEE International Symposium on , pp.1-4, 23-25 April 2012.
  29. Tao Lin, Sheqin Dong, Song Chen, and Satoshi Goto, “Linear Optimal One-Sided Single-Detour Algorithm for Untangling Twisted Bus”, ACM/IEEE Asia and South Pacific Design Automation Conference (ASP-DAC), 2012.
  30. Song Chen, Yuan Yao, Takeshi Yoshimura, “Mobility Overlap-Removal Based Timing-Constrained Scheduling”, IEEE International Conference on ASIC (ASICON), Xiamen, China, October, 2011.
  31. Xiaolin Zhang, Zhi Lin, Song Chen, and Takeshi Yoshimura, “An Efficient Level-shifter Floorplanning Method for Multi-Voltage Design”, IEEE International Conference on ASIC (ASICON), Xiamen, China, October, 2011.
  32. Jianchang Ao, Sheqin Dong, Song Chen, and Satoshi Goto, “Through-Silicon-Via Assignment for 3D-ICs”, IEEE International Conference on ASIC (ASICON), Xiamen, China, October, 2011.
  33. Wei Zhong, Song Chen, Fei Ma, Takeshi Yoshimura, and Satoshi Goto, “Floorplanning driven network-on-chip synthesis for 3-D SoCs,” in Proc. of IEEE International Symposium on Circuits and Systems (ISCAS), Brazil, pp. 1203-1206, 2011.
  34. Nan Liu, Song Chen, T. Yoshimura, Liu, "Floorplanning for high utilization of heterogeneous FPGAs," 12th IEEE International Symposium on Quality Electronic Design (ISQED), 2011, pp.1-6, 14-16 March 2011, doi:10.1109/ISQED.2011.5770736
  35. Wei Zhong, Bei Yu, Song Chen, T. Yoshimura, Sheqin Dong, S. Goto, "Application-specific Network-on-Chip synthesis: Cluster generation and network component insertion," 12th IEEE International Symposium on Quality Electronic Design (ISQED), pp.1-6, 14-16 March 2011, doi: 10.1109/ISQED.2011.5770718.
  36. Tao Lin, Sheqin Dong, Song Chen, Yuchun Ma, Ou He, S. Goto, "Novel and efficient min cut based voltage assignment in gate level," 12th IEEE International Symposium on Quality Electronic Design (ISQED), pp.1-6, 14-16 March 2011.
  37. B. Yu, S. Dong, Y. Ma, T. Lin, Y. Wang, Song Chen and S. Goto, “Network Flow-based Simultaneous Retiming and Slack Budgeting for Low Power Design”, In ACM/IEEE Asia and South Pacific Design Automation Conference (ASP-DAC), pp.1-6, Yokohama, Japan, 2011.
  38. B. Yu, S. Dong, Song Chen, and S. Goto, “Floorplanning and topology generation for application-specific network-on-chip”, In IEEE Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 535 –540, 2010.
  39. T. Lin, S. Dong, B. Yu, Song Chen, and S. Goto, “A revisit to voltage partitioning problem”, In Proceedings of the 20th ACM Great lakes symposium on VLSI, pp. 115--118. New York, NY, USA, 2010.
  40. Wei Zhong, Song Chen, and T. Yoshimura. Whitespace Insertion for Through-Silicon Via Planning on 3-D SoCs. In Proc. IEEE International Symposium on Circuits and Systems (ISCAS), pages 913--916. Paris, France, May 2010.
  41. J. Liang, Song Chen, and T. Yoshimura, “Redundant via insertion based on conflict removal,” in Proc. Of IEEE International Conference on Solid-State and Integrated-Circuit Technology (ICSICT). Nov. 2010, pp. 794-796.
  42. R. Liu, Song Chen, and T. Yoshimura, “Post-scheduling frequency assignment for energy-efficient high-level synthesis,” in Proc. IEEE Asia Pacific Conference on Circuits and Systems, Dec. 2010, pp. 588-591.
  43. Song Chen, Y. Yao, and T. Yoshimura, “A dynamic programming based algorithm for post-scheduling frequency assignment in energy-efficient high-level synthesis,” in International Conference on Solid-State and Integrated-Circuit Technology (ICSICT), Shanghai, China, Nov. 2010, pp. 797-799.
  44. Song Chen, Z. Xu, and T. Yoshimura, “A generalized v-shaped multilevel method for large scale floorplanning,” in The 9th IEEE International Symposium on Quality Electronic Design (ISQED), San Jose, CA, USA , March 2009, pp 734-739.
  45. W. Guo, Song Chen, M.-F. Chiang, J.-W. Shen, and T. Yoshimura. Convex-cost flow based redundant-via insertion with density-balance consideration. In Proc. IEEE International Conference on ASICs (ASICON), pp. 1280 --1283. 20-23 2009.
  46. X. Zhang, Song Chen, L. Piao, and T. Yoshimura. A heuristic method for module sizing under fixed-outline constraints. In Proc. IEEE International Conference on ASICs (ASICON), pages 738 --741. 2009.
  47. J.-W. Shen, M.-F. Chiang, Song Chen, W. Guo, and T. Yoshimura. Redundant via allocation for layer partition-based redundant via insertion. In Proc. IEEE International Conference on ASICs (ASICON), pp. 734 --737. 2009.
  48. B. Yu, S. Dong, S. Goto, and Song Chen, “Voltage-island driven floorplanning considering level-shifter positions”, In Proceedings of the 19th ACM Great Lakes symposium on VLSI (GLSVLSI ), pp. 51--56. New York, NY, USA, 2009.
  49. L. Ge, Song Chen, and T. Yoshimura. “Automatic implementation of arithmetic functions in high-level synthesis”, In Proc. 9th IEEE International Conference on Solid-State and Integrated-Circuit Technology (ICSICT), pp.2349 –2352, 2008.
  50. L. Ge, Song Chen, and T. Yoshimura. “High-speed, pipelined implementation of squashing functions in neural networks.” In Proc. 9th IEEE International Conference on Solid-State and Integrated-Circuit Technology (ICSICT), pp.2204 –2207, 2008.
  51. J. Lu, Song Chen, and T. Yoshimura, “Performance-maximized inter-layer via planning for 3d ics,” in Proc. IEEE International Conference on ASICs (ASICON), 2007, pp. 1096–1099.
  52. Song Chen and T. Yoshimura, “A stable fixed-outline floorplanning method,” in Proc. ACM International Symposium on Physical Design (ISPD), Austin,Texas, USA, March 2007. pp.119-126.
  53. Song Chen and T. Yoshimura, “On the number of 3-d ic floorplan configurations and a solution perturbation method with good convergence,” in Proc. IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), Singapore, December 2006.
  54. H. Bai, S. Dong, X. Hong, and Song Chen, “Buffer planning based on block exchanging,” in Proc. IEEE International Symposium on Circuits and Systems (ISCAS), Island of Kos, Greece, May 2006, pp. 5607–5610.
  55. Y. Ma, X. Hong, S. Dong, Song Chen, and C.-K. Cheng, “Buffer planning algorithm based on partial clustered floorplanning,” in Proc. IEEE International Symposium on Quality of Electronic Design (ISQED), San Jose, CA, USA, March 2005, pp. 213–218.
  56. Y. Ma, X. Hong, S. Dong, Song Chen, and C.-K. Chen, “Performance constrained floorplanning based on partial clustering,” in Proc. IEEE International Symposium on Circuits and Systems (ISCAS), vol. 2, Kobe, Japan, May 2005, pp. 1863–1866.
  57. Z. Zhou, S. Dong, X. Hong, Q. Hao, and Song Chen, “Analog constraints extraction based on the signal flow analysis,” in IEEE International Conference On ASIC, vol. 2, Shanghai, China, November 2005, pp. 825–828.
  58. Song Chen, S. Dong, and X. Hong, “A new interconnect-aware floorplan representation and its application to floorplanning targeting buffer planning,” in Proc. 48th IEEE Midwest Symposium on Circuits and Systems (MWCAS), vol. 2, Cincinnati, Ohio, USA, August 2005, pp. 1071–1074.
  59. Song Chen, X. Hong, S. Dong, and et al, “Floorplanning with consideration of white space resource distribution for repeater planning,” in Proc. Sixth International Symposium on Quality of Electronic Design (ISQED), San Jose, CA, USA, March 2005, pp. 628–633.
  60. Song Chen, X. Hong, S. Dong, Y. Ma, and C.-K. Cheng, “Vlsi block placement with alignment constraints based on corner block list,” in Proc. IEEE International Symposium on Circuits and Systems (ISCAS), vol. 6, Kobe, Japan, May 2005, pp. 6222–6225.
  61. Hongjie Bai, Sheqin Dong, Xianlong Hong, Song Chen, “A New Buffer Planning Algorithm Based on Room Resizing”, Embedded and Ubiquitous Computing EUC 2005, Lecture Notes in Computer Science Vol. 3824, pp. 291-299.
  62. Song Chen, X. Hong, S. Dong, Y. Ma, and et al, “A buffer planning algorithm with congestion optimization,” in Proc. ACM/IEEE Asia and South Pacific Design Automation Conference (ASPDAC), Yokohama, Japan, January 2004, pp. 615–620.
  63. Q. Hao, S. Dong, Song Chen, X. Hong, and et al, “Constraints generation for analog circuits layout,” in Proc. IEEE International Conference on Communications, Circuits and Systems, vol. 2, Chengdu, China, June 2004, pp. 1339–1343.
  64. Y. Ma, X. Hong, S. Dong, Song Chen, and et al, “Buffer allocation algorithm with consideration of routing congestion,” in Proc. ACM/IEEE Asia and South Pacific Design Automation Conference, Yokohama, Japan, January 2004, pp. 621–623.
  65. N. Xu, Song Chen, X. Hong, and S. Dong, “Thermal constraints for bbl placement,” in Proc. IEEE International Conference on Communications, Circuits and Systems, vol. 2, Chengdu, China, June 2004, pp.1253–1256.
  66. Y. Ma, X. Hong, S. Dong, Song Chen, and Y. Cai, “Dynamic global buffer planning optimization based on detail block locating and congestion analysis,” in Proc. ACM/IEEE Design Automation Conference (DAC), Anaheim, CA, USA, June 2003, pp. 806–811.
  67. Y. Ma, X. Hong, S. Dong, and Song Chen, “An integrated floorplanning with an efficient buffer planning algorithm,” in Proc. ACM International Symposium on Physical Design (ISPD), Monterey, CA, USA, April 2003, pp. 136–142.
  68. Y. Ma, X. Hong, S. Dong, Y. Cai, Song Chen, and et al, “Arbitrary convex and concave rectilinear block packing based on corner block list,” in Proc. IEEE International Symposium on Circuits and Systems (ISCAS), vol. V, Bangkok, Thailand, May 2003, pp. V–493 – V–496.
  69. S. Dong, X. Hong, Song Chen, and et al, “Solution space smoothing with five smoothing functions for vlsi module placement,” in Proc. IEEE International Conference on ASIC, vol. 1, Beijing, China, October 2003, pp. 132–135.
  70. S. Dong, X. Hong, X. Qi, R. Wang, Song Chen, and J. Gu, “Vlsi module placement with pre-placed modules and considering congestion using solution space smoothing,” in Proc. ACM/IEEE Asia and South Pacific Design Automation Conference (ASP-DAC), Kitakyushu, Japan, January 2003, pp.741–744.
  71. Song Chen, X. Hong, S. Dong, and et al, “Evaluating a bounded slice-line grid assignment in o(nlogn) time,” in Proc. IEEE International Symposium on Circuits and Systems (ISCAS), vol. 4, Bangkok, Thailand, May 2003, pp. IV–708 – IV–711.
  72. Song Chen, X. Hong, S. Dong, and et al, “A buffer planning algorithm based on dead space redistribution,” in Proc. ACM/IEEE Asia and South Pacific Design Automation Conference (ASPDAC), Kitakyushu, Japan, January 2003, pp. 435–438.
  73. Song Chen, X. Hong, S. Dong, and et al, “An o(nloglogn) algorithm for evaluation of bounded slice-line grid,” in Proc. IEEE International Conference on ASIC, vol. 1, Beijing, China, October 2003, pp. 208–211.

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