z
集成电路自动化设计方法 (Design Automation of VLSI) |
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
上课时间:2015秋季学期 星期四 4,5 9:45AM - 11:20AM | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
上课地点:3A303 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
实验时间地点:西区学生活动中心一楼信息科学实验中心训练基地。 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
助教:冯淦, email:fga@mail.ustc.edu.cn | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
答疑时间: 周四 2:00PM - 3:00PM,科技实验楼西楼720,或发邮件至songch@ustc.edu.cn | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
电话:0551-63602675 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Schedule [lecture notes are downloadable inside the campus]The slides will be updated before each lecture. |
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Lecture | Date | Topic | Slides | Readings | Assignments | Due |
1 | Sept. 10, 2015 | Guidance | ppt pdf | [1].Chapter 1 | ||
2 | Sept. 17, 2015 | Design Methodologies | ppt pdf | [1].Chapter_14 | Server.Login.Tutorial | |
3 | Sept. 24, 2015 | Verilog Basics and RTL Simulation | ppt pdf | Lab 1: Tutorial | ||
- | Oct. 2, 2015 | |||||
4 | Oct. 8, 2015 | High-level Synthesis | ppt pdf | Lab 2: Tutorial | ||
5 | Oct. 15, 2015 | Timing | ppt pdf | [1].Chapter_10 | ||
6 | Oct. 22, 2015 | Static Timing Analysis | ppt pdf | STA-NanoCircuits.A.Practical.Method | Lab 3: Tutorial | |
7 | Oct. 29, 2015 | Logic Synthesis | ppt pdf | [2].Chapter 6.3 | Lab 4: Tutorial | |
8 | Nov. 5, 2015 | Power | ppt pdf | [1].Chapter 5 | Lab 5: Tutorial | |
9 | Nov. 12, 2015 | Delay | ppt pdf | [1].Chapter 4 | ||
10 | Nov. 19, 2015 | Physical Design | ppt pdf | [2].Chapter 10-13 | Lab 6: Tutorial |
[1]. Meil H. E. Weste and David Money Narris, "CMOS VLSI Design: A circuits and Systems Perspective , fourth edition, Addison-Wesley. Web Enhanced
[2]. Wang, Chang, and Cheng (Ed.), Electronic Design Automation: Synthesis, Verification, and Test, Chapter 5-6, 10-13, Morgan Kaufmann, 2009.
[3]. David A. Patterson and John L. Hennessy, Computer Organization and Design: The hardware/software interface, 4th edition, Appendix C, Chapter 3, Chapter 4. Link
All the above electoric resources are available here
The following references are for labs
[4]. VCS Documents (Simulation)
[5]. Design Compiler Documents (Logic Design)
[6]. Unix Tutorial for Beginners VI Help EMACS Help Server.Login.Tutorial
[7]. IEEE Std 1364-2005. Verilog Hardwar Description Language. Piscataway, New Jersey: The IEEE Computer Society, 2005. [Revised in 2001 and reaffirmed, with System Verilog added compatibility, in 2005. If you plan to do any serious work in verilog, you should have a copy of the standard. It is not oly normative, but it includes numerous examples and explanatory notes concering every detail of the language.]
[8]. IEEE Std 1800-2012. IEEE Standard for SystemVerilog— Unified Hardware Design, Specification, and Verification Language. (Revision of IEEE Std 1800-2009) The IEEE Computer Society and the IEEE Standards Association Cooperate Advisory Group, 2013.
[9]. Thomas and Moorby, The Verilog Hardware Description Language, fifth edition, Kluwer Academic publishers, 2002.
[10]. IC Compiler Documents(Physical Design)