超大规模集成电路设计优化 (VLSI Design Optimization) |
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| 上课时间：星期三 上午 3,4,5 9:45-12:10 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 上课地点：3A311 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 答疑时间：周三 14:00 - 15:00，科技实验楼西楼720，或发邮件至songch@ustc.edu.cn | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 电话：0551-63602675 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Schedule [lecture notes are downloadable inside the campus,(2013 Spring)] |
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NEW: Final Examination: June 18, Wednesday 3,4,5, 3A311. |
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NEW: Course Project Presentation: June 11, Wednesday, 3,4,5. |
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NEW: Guideline for Course Project Proposal Updated (download) Due: May 25 |
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| Lecture | Date | Topic | Slides | References | Assignments | Due |
| 1 | February 19, 2014 | Guidance, Design Methodologies | ppt pdf | [4].Chapter_14 | ||
| 2 | February 26, 2014 | Electronic System Level-design and High-level Synthesis | ppt pdf | [2].Chapter5 | ||
| 3 | March 5, 2014 | Timing | ppt pdf | [4].Chapter_10 | ||
| 4 | March 12, 2014 | Static Timing Analysis (STA) | ppt pdf | STA-NanoCircuits.A.Practical.Method | Verilog.Basics&Lab.Tutorial | |
| 5 | March 19, 2014 | RTL Simulation & Logic Optimization | ppt pdf | [2].Chapter_6 , Nonblocking.Assignments | ||
| 6 | March 26, 2014 | Technology Mapping | ppt pdf | [2].Chapter_6, [1].Chapter 1 | ProblemSet01(doc pdf ) | |
| 7 | April 2, 2014 | Delay (Gate&Wire) | ppt pdf | [4].Chapter4.3 and Chapter 6 | ||
| 8 | April 9, 2014 | Power | ppt pdf | [4].Chapter5 | ||
| 9 | April 16, 2014 | Chip Planning | ppt pdf | [1].Chapter_3, [2].Chapter_10 | ||
| 10 | April 23, 2014 | Netlist and System Partitioning | ppt pdf | [1].Chapter_2 | ||
| 11 | April 30, 2014 | Placement | ppt pdf | [2].Chapter11 [1].Chapter4 Placement-Examples | ||
| 12 | May 7, 2014 | Routing I | ppt pdf | [2].Chapter12, [1].Chapter5 Routing-Examples-1 | ||
| 13 | May 14, 2014 | Routing II | ppt pdf | [2].Chapter12 | Lab2: Synopsys Ref Logic Design Flow Tutorial | |
| 14 | May 21, 2014 | Routing III | ppt pdf | [2].Chapter13.3 [4].Chapter 13 Routing-Examples-2 | Guideline.for.Course.Project.Proposal Project Resources | May 25 |
| 15 | May 28, 2014 | Clock Routing & Summary | ppt pdf | [2].Chapter13.4, [3], [2].Chapter12.6 |
[1]. Sung Kyu Lim, Practical Problems in VLSI Physical Design Automation, Springer, 2008.
[2]. Wang, Chang, and Cheng (Ed.), Electronic Design Automation: Synthesis, Verification, and Test, Morgan Kaufmann, 2009.
[3]. Chang and Chen, “Design for Manufacturability and Reliability,” IEEE Circuits and Systems Magazine, Sep. 2009.
[4]. Meil H. E. Weste and David Money Narris, "CMOS VLSI Design: A circuits and Systems Perspective", fourth edition, Addison-Wesley
All the above electoric resources are available here
The following references are for labs
[5]. VCS Documents (Simulation)
[6]. Design Compiler Documents(Logic Design)
[7]. Unix Tutorial for Beginners VI Help EMACS Help Server.Login.Tutorial
[8]. IEEE Std 1364-2005. Verilog Hardwar Description Language. Piscataway, New Jersey: The IEEE Computer Society, 2005. [Revised in 2001 and reaffirmed, with System Verilog added compatibility, in 2005. If you plan to do any serious work in verilog, you should have a copy of the standard. It is not oly normative, but it includes numerous examples and explanatory notes concering every detail of the language.]
[9]. IC Compiler Documents(Physical Design)
[10]. Parameterized Models Using Verilog 2001
[11]. RTL Coding Styles That Yield Simulation and Synthesis Mismatches
[12]. Project Resources