VLSI Architecture & CAD Lab

1. High-performance Low Power On-Chip Interconnect Network Design, USTC Initiative Funding, 2012.9-2015.8. (PI)
2. Application-Specific On-Chip Communication System Design using RF-Interconnects, the Fundamental Research Funds for the Central Universities at USTC, 2013.1-2014.12. (PI)
3. Architecture Synthesis for Low Power Application-Specific Network-on-Chips with RF Interconnect, NSFC, 2015.1~2017.12. (PI)
4. Architecture Synthesis for Dynamically Reconfigurable Application-Specific Network-on-Chips, NSFC, 2017.1~2017.12. (PI)
5. Large scale neuromorphic networks based on memristor for brain-inspired computing architecture, NSFC (State Key Program), 2018.1~2022.12. (Participant @USTC)
6. Synthesizing Brain Network inspired On-Chip Interconnection Network for Large Scale Neuromorphic Computing Systems, NSFC, 2019.1~2022.12. (PI)

Created: 2014 July,