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Combining Ant System Algorithm and Simulated Annealing for 3D/2D Fixed-Outline Floorplanning

We proposed a two-phase algorithm for 3D/2D Fixed-Outline Floorplanning with minmization of wirelength and through silicon vias. The AS algorithm is used to globally generate solutions in the first phase, which are then improved by the SA-based searching algorithm in the second phase. During AS phase, a probability layer assignment strategy is proposed to determine the layer assignment of blocks. Compared with some previous fixed-outline floorplanners, two-phase algorithm is very effective.

Downloadable Binary File (64bit Linux binary): 2d, 3d

References

  1. Qi Xu, Song Chen, and Bin Li. Combining the Ant System Algorithm and Simulated Annealing for 3D/2D Fixed-Outline Floorplanning. Applied Soft Computing (link), accepted, 2015.

IARFP: A Fixed-Outline Floorplanner

Compared with some previous fixed-outline floorplanners, IARFP is very effective and has good scalability. Experiments shows that, if area and wirelength are optimized simultaneously, using less running time IARFP obtains 94.24% average success rate, compared to the average success rates of 67.2% and 31% obtained by Parquet 4.5 and the B*-tree based fixed-outline floorplanner (NTU-FP) , respectively. At the same time, IARFP reduces the wirelength with fixed-outline constraint by 21% and 19%, respectively, compared with Parquet 4.5 and NTU-FOFP [1].

Download (32bit Linux binary)

References
  1. S. Chen and T. Yoshimura, "Fixed-outline floorplanning: Enumerating block positions and a new objective function for calculating area costs", IEEE Transactions On Computer-Aided Design of Integrated Circuits and Systems, vol.27, no.5, pp.858-871, 2008.
  2. S. Chen and T. Yoshimura, "A stable fixed-outline floorplanning method", in Proc. ACM International Symposium on Physical Design, Austin,Texas, USA, March 2007.

IAR-MLFP: A Multi-layer Fixed-Outline Floorplanner for Three Dimensional ICs

3D (stacked device layers)ICs can significantly alleviate the interconnect problem coming with the decreasing feature size and ispromising for heterogeneous integration. In this paper, we concentrateon the configuration number and fixed-outline constraints in the floorplanning for 3D ICs. Extended sequence pair, named partitioned sequence pair (in short, P-SP), is used to represent 3D IC floorplans. We prove that thenumber of configuration of 3D IC floorplans represented by P-SP is less than that of planar floorplans represented by sequence pair (SP) and decreases as the device layer number increases.

Download (32bit Linux binary)

References
  1. Song Chen and T. Yoshimura. Multi-layer floorplanning for stacked ICs: Configuration number and fixed-outline constraints. Integration, the VLSI journal, 43(4), pp.378-388, 2010. binary package

Created: 2014 July,