超大规模集成电路设计优化 (VLSI Design Optimization) |
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 上课时间：星期四晚上 19:00-21:25 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 上课地点：3A210 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 答疑时间：周三 14:00 - 15:00，科技实验楼西楼720，或发邮件至songch@ustc.edu.cn | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 电话：0551-63602675 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Schedule [lecture notes are downloadable inside the campus,(2014 Spring)] |
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
|
NEW: Problems repository Problems for the examination in 2014. Project Resources & Guide for Project Proposals Optional Lab Tutorials: RTL Simulation & Logic Syntheis. For the first time to log in, please refer to Server.Login.Tutorial If you are new to the Unix/Linux-like OS, you can start here (Unix Tutorial for Beginners) Good Text Editors in Linux OS: VI Help EMACS Help |
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| Lecture | Date | Topic | Slides | References | Assignments | Reading | Due |
| 1 | March 12, 2015 | Guidance, Design Methodologies | ppt pdf | [3].Chapter_14, More than Moore | EDA-Where electronics begin(Video) | |
| 2 | March 19, 2015 | High-level Synthesis | ppt pdf | [2].Chapter5 | ||
| 3 | March 26, 2015 | High-level Synthesis II | ppt pdf | [5].Chapter 4.8, 5.6, [3].Chapter 10.2 | ||
| 4 | April, 2 | Verilog Basics & RTL Simulation | ppt pdf | Nonblocking.Assignments | Lab.Tutorial | |
| 5 | April 9, 2015 | Logic Synthesis | ppt pdf | [2].Chapter_6 | ||
| 6 | April 16, 2015 | Delay (Gate&Wire) | ppt pdf | [3].Chapter4.3 and Chapter 6 | ||
| 7 | April 23, 2015 | Statical Timing Analysis | ppt pdf | [3].Chapter 10.2, STA-NanoCircuits.Chapter 7, 8 | ||
| 8 | April 30, 2015 | Low Power Design Technologies | ppt pdf | [3].Chapter5 | ||
| 9 | May 7, 2015 | Chip Planning | ppt pdf | [1].Chapter_3, [2].Chapter_10 | ||
| 10 | May 14, 2015 | Netlist and System Partitioning | ppt pdf | [1].Chapter_2 | ||
| 11 | May 21, 2015 | Placement | ppt pdf | [2].Chapter11 [1].Chapter4 Placement-Examples | ||
| 12 | May 28, 2015 | Routing I | ppt pdf | [2].Chapter12, [1].Chapter5 Routing-Examples-1 | ||
| 13 | June 4, 2015 | Routing II | ppt pdf | [1].Chapter 6 Routing-Examples-1 | ||
| 14 | June 7, 2015 | Clock Routing & Summary | ppt pdf | [2].Chapter13.4, [3], [2].Chapter12.6 |
[1]. Sung Kyu Lim, Practical Problems in VLSI Physical Design Automation, Springer, 2008.
[2]. Wang, Chang, and Cheng (Ed.), Electronic Design Automation: Synthesis, Verification, and Test, Morgan Kaufmann, 2009.
[3]. Meil H. E. Weste and David Money Narris, CMOS VLSI Design: A circuits and Systems Perspective, fourth edition, Addison-Wesley
[4]. Chang and Chen, Design for Manufacturability and Reliability, IEEE Circuits and Systems Magazine, Sep. 2009.
[5]. G. De Micheli, Synthesis and optimization of digital circuits,McGraw Hill, 1994.
All the above electoric resources are available here
The following references are for labs
[5]. VCS Documents (Simulation)
[6]. Design Compiler Documents(Logic Design)
[7]. Unix Tutorial for Beginners VI Help EMACS Help Server.Login.Tutorial
[8]. IEEE Std 1364-2005. Verilog Hardwar Description Language. Piscataway, New Jersey: The IEEE Computer Society, 2005. [Revised in 2001 and reaffirmed, with System Verilog added compatibility, in 2005. If you plan to do any serious work in verilog, you should have a copy of the standard. It is not oly normative, but it includes numerous examples and explanatory notes concering every detail of the language.]
[9]. IC Compiler Documents(Physical Design)
[10]. Parameterized Models Using Verilog 2001
[11]. RTL Coding Styles That Yield Simulation and Synthesis Mismatches
[12]. Project Resources