超大规模集成电路设计优化 (VLSI Design Optimization) |
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| 上课时间：星期一上午 9:45-12:10 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 上课地点：3A110 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
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Schedule [lecture notes are downloadable inside the campus,(2015 Spring)] |
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NEW: Guideline for Course Project Proposal (download) Due: May 25 |
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| Lecture | Date | Topic | Slides | References | Assignments | Reading | Due |
| 1 | February 22, 2016 | Guidance, Design Methodologies | ppt pdf | [3].Chapter_14, More than Moore | EDA-Where electronics begin(Video) | |
| 2 | February 29, 2016 | High-level Synthesis I (Scheduling) | ppt pdf | [2].Chapter 5 | ||
| 3 | March 7, 2016 | High-level Synthesis II (Binding) | ppt pdf | [2].Chapter 5 | ||
| 4 | March 14, 2016 | High-level Synthesis III (Pipeline Scheduling) | ppt pdf | [5].Chapter 4.8, 5.6 | ||
| 5 | March 21, 2016 | Clocking/Sequencing | ppt pdf | [3].Chapter 10.1-10.3 | ||
| 6 | March 28, 2016 | Delay (Gate and Wire) | ppt pdf | [3].Chapter4.3 and Chapter 6 | ||
| - | April 4, 2016 | |||||
| 7 | April 11, 2016 | Logic Synthesis | ppt pdf | [2].Chapter_6 | ||
| 8 | April 18, 2016 | Low Power Design Technologies | ppt pdf | [3].Chapter5 | ||
| 9 | April 25, 2016 | RTL Description & Simulation | ppt pdf | STA-NanoCircuits.Chapter 7, 8 | Tutorials: RTL Simulation & Logic Syntheis | |
| - | May 2, 2016 | |||||
| 10 | May 9, 2016 | Netlist/System Partitioning and Chip Planning | ppt pdf | [1].Chapter 2, 3, [2].Chapter 10 | ||
| 11 | May 16, 2016 | Placement | ppt pdf | [2].Chapter11 [1].Chapter4 Placement-Examples | ||
| 12 | May 23, 2016 | Routing | ppt pdf | [2].Chapter12, [1].Chapter5 Chapter 6 Routing-Examples-1 | ||
| 13 | May 30, 2016 | Clock Routing & Summary | ppt pdf | [2].Chapter13.4, [3], [2].Chapter12.6 | ||
| 14 | June 6, 2016 | System C (Expected) | ||||
| 15 | June 13, 2016 | Final Examination | ||||
| 16 | June 20, 2016 | Course Project Check |
[1]. Sung Kyu Lim, Practical Problems in VLSI Physical Design Automation, Springer, 2008.
[2]. Wang, Chang, and Cheng (Ed.), Electronic Design Automation: Synthesis, Verification, and Test, Morgan Kaufmann, 2009.
[3]. Meil H. E. Weste and David Money Narris, CMOS VLSI Design: A circuits and Systems Perspective, fourth edition, Addison-Wesley
[4]. Chang and Chen, Design for Manufacturability and Reliability, IEEE Circuits and Systems Magazine, Sep. 2009.
[5]. G. De Micheli, Synthesis and optimization of digital circuits,McGraw Hill, 1994.
All the above electoric resources are available here
The following references are for labs
[5]. VCS Documents (Simulation)
[6]. Design Compiler Documents(Logic Design)
[7]. Unix Tutorial for Beginners VI Help EMACS Help Server.Login.Tutorial
[8]. IEEE Std 1364-2005. Verilog Hardwar Description Language. Piscataway, New Jersey: The IEEE Computer Society, 2005. [Revised in 2001 and reaffirmed, with System Verilog added compatibility, in 2005. If you plan to do any serious work in verilog, you should have a copy of the standard. It is not oly normative, but it includes numerous examples and explanatory notes concering every detail of the language.]
[9]. IC Compiler Documents(Physical Design)
[10]. Parameterized Models Using Verilog 2001
[11]. RTL Coding Styles That Yield Simulation and Synthesis Mismatches
[12]. Project Resources