超大规模集成电路设计优化 (VLSI Design Optimization) |
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| 上课时间：星期三上午 9:45-12:10 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 上课地点：3A306 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 电话：0551-63602675 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Schedule [lecture notes are downloadable inside the campus,(2016 Spring)] |
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| Lecture | Date | Topic | Slides | References | Assignments | Reading | Due |
| 1 | February 26, 2020 | Guidance, Design Methodologies | [1].Chapter_14 | IRDS 2018-Exective Summary | ||
| 2 | March 4, 2020 | High-level Synthesis I (Design Examples) | [6].Chapter 2, 4, [4].Appendix A | |||
| 3 | March 11, 2020 | High-level Synthesis II (Scheduling & Binding) | [2].Chapter 5, Chapter 6; [3].Chapter 5 | |||
| 4 | March 18, 2020 | High-level Synthesis III (Pipelining) | [3].Chapter 4.8, 5.6;[6].Chapter 4.6 | |||
| - | March 25, 2020 | No lecture | ||||
| 5 | April 1, 2020 | Clocking/Sequencing | [1].Chapter 10.1-10.3 | |||
| 6 | April 8, 2020 | Logic Synthesis | [3].Chapter 6, [4]. Chapter 1.2 | |||
| 7 | April 15, 2020 | Delay | [1]. Chapter 4.3, Chapter 6 | |||
| 8 | April 22, 2020 | Low Power Design Technologies | [1].Chapter5 | |||
| 9 | April 29, 2020 | RTL Description & Simulation | STA-NanoCircuits.Chapter 7, 8 | Tutorials: RTL Simulation & Logic Syntheis | ||
| 10 | May 6, 2020 | Chip Planning/Floorplanning | [4].Chapter 3, [3].Chapter 10 | |||
| 11 | May 13, 2020 | Placement | [3].Chapter11 [4].Chapter4 Placement-Examples | |||
| 12 | May 20, 2020 | Routing | [3].Chapter12, [4].Chapter 5, Chapter 6 Routing-Examples-1 | |||
| 13 | May 27, 2020 | Clock Routing, P/G Routing & Summary | [3].Chapter13, [5] | |||
| 14 | June 8, 2020 | Project Review |
[1]. Meil H. E. Weste and David Money Narris, CMOS VLSI Design: A circuits and Systems Perspective, fourth edition, Addison-Wesley
[2]. G. De Micheli, Synthesis and optimization of digital circuits,McGraw Hill, 1994.
[3]. Wang, Chang, and Cheng (Ed.), Electronic Design Automation: Synthesis, Verification, and Test, Morgan Kaufmann, 2009.
[4]. Sung Kyu Lim, Practical Problems in VLSI Physical Design Automation, Springer, 2008.
[5]. Chang and Chen, Design for Manufacturability and Reliability, IEEE Circuits and Systems Magazine, Sep. 2009.
[6]. David A. Patterson and John L. Hennessy, Computer Organization and Design, Morgan Kaufmann Publishers, 2018.
All the above electoric resources are available here
The following references are for labs
[7]. VCS Documents (Simulation)
[8]. Design Compiler Documents(Logic Design)
[9]. Unix Tutorial for Beginners VI Help EMACS Help Server.Login.Tutorial
[10]. IEEE Std 1364-2005. Verilog Hardwar Description Language. Piscataway, New Jersey: The IEEE Computer Society, 2005. [Revised in 2001 and reaffirmed, with System Verilog added compatibility, in 2005. If you plan to do any serious work in verilog, you should have a copy of the standard. It is not oly normative, but it includes numerous examples and explanatory notes concering every detail of the language.]
[11]. IC Compiler Documents(Physical Design)
[12]. Parameterized Models Using Verilog 2001
[13]. RTL Coding Styles That Yield Simulation and Synthesis Mismatches
[14]. Project Resources